1. Field of the Invention
This invention relates to a method for fabricating a power transistor, more particularly to a method for fabricating a power transistor having a super junction.
2. Description of the Related Art
FIG. 1 illustrates a semiconductor device including a plurality of conventional power transistors, each of which includes a substrate 11, a main body region 12, a source region 13, a well region 14, and a gate structure 15.
The substrate 11 is epitaxially formed, has a first electrical type, and includes a lower portion 112, an upper portion 113, and a trench 111 that is indented from a top face of the upper portion 113 to reach the lower portion 112.
The main body region 12 and the well region 14 have the second electrical type, and are filled in the trench 111. The well region 14 is formed on and contacts the main body region 12. The source region 13 has the first electrical type and contacts the well region 14 and/or the main body region 12 so as to be separated from the substrate 11. An interface between the substrate 11 and the main body region 12 defines a super junction.
When the first electrical type is n-type, the second electrical type is p-type. On the contrary, when the first electrical type is p-type, the second electrical type is n-type.
The gate structure 15 is disposed on the top face of the upper portion 113, and includes a dielectric layer 151 formed on the top face of the upper portion 113, and a conductive layer 152 formed on the dielectric layer 151 and is spaced apart from the substrate 11 by the dielectric layer 151. The dielectric layer 151 is made of an insulative material, such as silicon dioxide or silicon nitride. The conductive layer 152 is made of a conductive material, such as metal or polycrystalline silicon.
The lower portion 112 of the substrate 11 serves as a drain, the well region 14 serves as a well, the source region 13 serves as a source, and the gate structure 15 serves as agate. The lower portion 112, the gate structure 15 and the source region 13 are adapted to receive electrical power from external circuit devices so that the power transistor can generate an electrical field using voltage differences.
When a predetermined voltage is applied on the conductive layer 152 of the gate structure 15 and the substrate 11 relative to the source region 13, the electrical charges from the lower portion 112 of the substrate 11 pass through the well region 14 and the source region 13 to forma conductive channel so that the power transistor actuates when the predetermined voltage is applied.
The conventional power transistor is formed by the following steps. Firstly, the substrate 11 is epitaxially grown to have the first electrical type and to include the lower portion 112 and the upper portion 113, and the upper portion 113 is etched to form the trench 111 therein.
Next, the trench 111 is filled with a filling material having the second electrical type using an epitaxial process. Thereafter, the dielectric layer 151 and the conductive layer 152 are sequentially formed on the top face of the upper portion 113 to form the gate structure 15.
An ion implantation process is conducted using the conductive layer 152 as a mask. To be specific, second electrical type carriers are implanted into the filling material in the trench 111 so as to form a well-forming region that is implanted with the second electrical type carriers, and the main body region 12 that is not implanted with the second electrical type carriers. Then, first electrical type carriers are implanted in the well-forming region so as to form the source region 13 that has the first electrical type, and the well region 14 that has the second electrical type.
However, since the trench 111 is formed by etching, the super junction between the substrate 11 and the main body region 12 is likely to be uneven, and thus is not crystal lattice continuous interface and has lattice defects. This may affect the transmission of the electrical charges when the power transistor is operated. Besides, because the super junction between the substrate 11 and the main body region 12 is a heterogeneous interface, the electrical charges may be trapped and accumulated in the super junction. Therefore, leakage current may occur when the power transistor is standby, and thus, the conventional power transistor may have poor current stability and reliability.